`include "defines.v"
module mem_filter (
    input wire              rst,

    input wire [ 7 : 0]     mem_w_mask_i,
    input wire [`REG_BUS]   mem_w_data_i,
    input wire              mem_w_en_i,
    output reg [`REG_BUS]   mem_r_data_o,
    input wire [`REG_BUS]   mem_addr_i,
    input wire              mem_ce_i,

    output wire [ 7: 0]     mem_w_mask_o,
    output wire [`REG_BUS]  mem_w_data_o,
    output wire             mem_w_en_o,
    output wire [`REG_BUS]  mem_addr_o,

    input wire [`REG_BUS]   ram_r_data_i,
    output wire             ram_ce_o,

    input wire [`REG_BUS]   clint_r_data_i,
    output wire             clint_ce_o,

    output                  skip_o
);
    wire   clint_addr_flag;
    assign clint_addr_flag = (mem_addr_i >= 64'h200_0000) && (mem_addr_i <= 64'h200_BFFF);

    assign mem_w_mask_o   = mem_w_mask_i;
    assign mem_w_data_o   = mem_w_data_i;
    assign mem_w_en_o     = mem_w_en_i;
    assign mem_addr_o     = mem_addr_i;
    assign ram_ce_o       = clint_addr_flag == 1'b0 ? mem_ce_i : 1'b0;

    assign clint_ce_o     = clint_addr_flag == 1'b1 ? mem_ce_i : 1'b0;

    assign mem_r_data_o   = clint_addr_flag == 1'b0 ? ram_r_data_i : clint_r_data_i;

    assign skip_o = mem_ce_i == 1'b1 && clint_addr_flag == 1'b1 ? 1'b1 : 1'b0;
endmodule
